ROLAND SDE 2000

Page 1

APR.15,1982 SDE-2000

SDE-ZOOO SERVICE NOTES Am25L04

F l 751- Ed; [10 Low-Power, Twelve-Bit Successive Approximation Registers

LOGIC DIAGRAMS

r'
|Bits9tol

l
|

SPECIFICATIONS
* DIGITAL DELAY * SDE-ZOOO
Input Level +4 dBm (+29 dBm max)
-20 dBm (+5 dBm max)
Impedance 56H)
Output Level +4 dBm (+13 dBm max) into 6009 load CONNEQESEJIAG RAM E E] 1 . 2,, 3 we
-20 dBm (-8 dBm max) into IOkQ load DO I: 3 511
. . 55 i: 3 N0
Impedance 1009 at +4 dBm position 00 C 3 011
6509 at -20 dBm position, Mixed 01 C :I 010
5500 at -20 dBm position, Delay 02 I: j 09
03 I: :I 08
Feedback Send Level : +4 dBm (+16 dBm max) 04 E :1 Q7
Impedance: 1000 05 C j 06
Nc I: 3 NC
Return Level : +4 dBm (+19 dBm max) D I: :1 g
Impedance : 78kt? GND I: 12 13 :1 CP
CV In Modulation CV Operation Voltage : 0 to +10V (i20V, allowable)
Impedance : QOkSZ
General Delay Time 0 to 320 ms The registers consist of a set of master latches that act as the control elements in the device and change state
Performance 0 to 540 "5 (in 1 m5 51395) when the input clock is LOW, and s set of slave latches that hold the register data and change on the input clock
Delay Accuracy i0,5% LOW-to-HIGH transition. The device accepts data at the D input of the register and sends the data to the
. appropriate slave latch to appear at the register output (and the DO output) when the clock goes from
Frequency Response i8 3: :3 igitlgz :g:571-g%§ta?lfr):iay, 0 to 320 ms LOW-to-HIGH. At the same time that data enters the register bit the next less significant bit is set to a LOW
10 Hz to 7.2 kHz +0.5, -3 dB at Delay, Oto 640 ms ready for the next iteration. The register is reset by holding the S (Start) signal LOW during the clock
5' I N . R f LOW-to-HIGH transition. The register synchronously resets to the state 011 LOW, and all the remaining register
((filaAtfat fest; 1:131) 90 dB, Direct outputs HIGH. The CC (Conversion Complete) signal is also set HIGH at this time. After the clock has gone
& output 90 dB, Delay HIGH resetting the register, the S signal is removed. 0n the next clock LOW-to-HIGH transition the data on
Dynamic Range (IHF A) Greater than 112 dB, Direct the D Input is set into the 011 register bit and the 010 register bit is set to a LOW ready for the next clock
90 dB, Delay cycle. On the next clock LOW-to.HlGH transition data enters the 010 register bit and 09 is set to a low. This

. . _ operation is repeated for each register bit in turn until the register has been filled. When the data goes into 00,
Total Harmonic Distortion

at rated input 8: output Less than 0.05%, Direct the CC signal goes LOW, and the register is inhibited from further change until reset by a Start-signal.
Ref. 1 kHz 0.08% typ, 0.2% max, Delay

Power 27W(117V), 30W(220V, 240V)

Consumption

Dimensions 482(W) x 47(H) x 355(D) mm (19 x 1.85 x 14 in.)

19 (ElA-lU) rack mount

Weight 55¢ (12 lbs.)

@Roland Printed in Japan B-3 1