ROLAND CSQ 100

Page 2

CSQ-100 MAY 31,1979
I PD8048 Pin Description

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as B 5;
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4: o
a a
Pin 8 E
Designation No. Function
I
DB DBO 12 - E E
(Data bus) 1 13 S . CV and E g a3
a 14 mm GATE data gg
3 15 scanning during
A: 16 CV data RAM RAM address #1
-LED address a
5 17 Egg
6 18- (/2 L1:
7 19 Output Gate signal
:2:
P1 P10 27 a
(Port 1) 11 28 RAM address 00 j
12 29 O
l} 30 RAM address Ia r83-
14 31 LED timing 159 5'3
15 32 Output CV s/H and Gate hold timing -: OE H
16 33
. t .
l? 34 Metronome tlmlng §§ E g
P2 P20 21 00 <1
(Port 2) E H mg
21 22 <
22 23 CV 11" by-pass enable during the STOP mode I I?
LH
22 i2- 3 a s N
. . , _ a a1 5 94 3 H e
25 36 Read sw1tches status during sw1tch seaming o g E 91 a ('3'
26 37 V
27 38- 5 '__ N 1900
RESET 4 Input to reset the 8048 when power is on o g
HIT 6 External gate input _I g
TO 1 Digital data input suting A-D conversion m a 3 E
T1 39 Accepts TEMPO clock output a g E
V
XTAL l 2 External source inputs for internal oscillator 00 b
XTAL 2 3 1
(Top View) I
To 1 Vcc<+5V) .-( 1-0 N Oco a g o M
XTAL] 2 1: The uPD8048 is an 8-bit parallel a g g 38 a E? g 8 E-N-E
XTALZ 3 P27 computer fabricated on a single H 3 8 8 ' E 2 a g :5
RES; 2 :2 sillicon chip. The 8048 contains a m
S
m 6 P24 lk x 8 ROM program memory, 27 1/0 3
EA 7 p17 lines, an 8-bit timer/counter and no 3
RE 3 P16 clock circuits. 2 Q
FSEN 9 P15 Used in the 030-100 is a uPD80480- B 8
W 10 PM t . .
028 vers1on in which program and
ALE n #PD8048C P13 ,
DB 12 P12 data dedicated to the CSQ-lOO are
DB? 13 p stored in the program memory.
D32 14 P10 g z >2
DBu v...,<+5w E H OH
034 FROG
DB5 P23
D36 P22
DB7 P21
(0V)Vss P20

.v

Page 3

MAY 31,1979 030-100

{ Start ) CIRCUIT DESCRIPTION

This description is divided into parts:

the general description which explains
roughly the functions of CSQ-lOO, and

LOAD I PLAY the detailed description which centers
rm____w_hi.____<§\§fi:ih méigy around A/D and D/A converters since
, . .
A/D r/// jRead these are practically the heart in
vSTOP . RAM > this instrument.
| Complete unserstanding of A/D and D/A
///// conversion circuits will aid in per-
////////E / KCV forming adjustments in Section II.
any 83 < ADD>
pressed? \x\
\/
lYes OFF
I See
; page 6 Function of " One chip computer"
. I
Write CV Write Write l Pass CV ! Add 24 ADD ON uPD8048
. CV GATE
giige t and into (Q132 on) CSQ-lOO performes its functions with uPD-
a a
constant 32$? RAM 8048 at the center position for all, in-
fit§ RAM cluding the following in its performance
Wice
METRONOME) cycles:
into RAM A/D

1. Switch Scanning

2. D/A Conversion

,3. A/D Conversion
4. Write/Read of Data to or from
External RAM
- 5. Timing for lighting LED Indicator
D/A /?9 6. 'Triggering of METRONOME
7. Holding of GATE OUT

Output result