Nad Viso One BT Service Manual

Page 39

IC BLOCK DIAGRAM
MCU - U1

Interrupt Dala BUS
Controller ( )
PORTA 1
16 ->
v 8 16 6 (13 l/Ol
PSV & Table Data Latch
Dam Access
Control Block Data RAM
Program Counter
Address
Stack Repeat Latch PORTB
Control Control +
Logic Logic A (161/0)
16
16
Address Latch Read AGU
Write AGU (1)
PORTC
Program Memory A
(8 I/O)
Dam Latch
Address Bus 16
m
E
E PORTD)
L *
Inst Latch g (16 VD)
InstRegister >
. +
33:55:" T (1)
Control _> d V FORTE
Divi e A »
OSCO/CLKO i ControlSignals Support 16x16 (10I/0)
OSCl/CLKI 17x17 W Reg Array I I
IXK" Timing Power-up Multiplier
Generation 0 Tlmer
Oscillator
REFO FRC/LPRC Start-up Timer PORTFil)
Oscillators .
EH Power-on 16-BItALU ->
Reset 16 (9 I/O)
Precision
Band Gap -> Watchdog fl
Reference Timer
ENVREG
Voltage BOR and
'2 Regulator LVDm l1)
PORTG
& lg & (12 HO)
VDDCORENCAP VoD,Vss MCLR
10-Elt
Timerl Timed/3(3) omen/5(3) Rch ADC Comparamrslzi usa OTG
I I I I I I 1 } PMP/PSP
'C PWM/OC 5P1 |2C UART
(1)
1-943) 1.95) 'C 5 1/26 3) 1/2/3 1/2/3/412) CTM U

Note 1: Notall I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: These peripheral IIOs are only accessible through remappable pins.

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Page 54

PACKING DIAGRAM & PARTS LIST

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