Mark levinson 27 5 pwr service manual

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The A085 PC Assembly contains buffer and voltage gain circuitry for the No.
27.5 Power Amplifier. Regulated DC Supplies and current gain circuitry are located on
the AC-8 PC Assembly and interconnected via gold pins.

BUFFER STAGE ONE

The buffer input stage consists of a bipolar cascoded differential amplifier with
passive collector loading and constant current source and sink for DC biasing. 050.
052 and R62 comprise a current sink for total first stage current of 2.4 mA. 800 pA
is available to each half of 064, a supermatch pair configured as a differential
common emitter amplifier. The remaining 800 uA is sourced by 062, 063 and R55 for
biasing of cascoded common base amplifiers 051 and 053 by CR68, CR69 and R61.

BUFFER STAGE TWO

The second buffer stage is comprised of a differential input amplifier, 055 and
059, with current mirror 056 and 058, for conversion to single-ended output. Half
of the differential amplifier is cascoded by 057 for isolation from driveline voltage
swings. Passive DC biasing is accomplished by R75, R76 and R77. Approximately 9
mA is available to each side of the differential amplifier, with 1 mA bias through R76
and R77 to set DC bias of 057's base.

BUFFER OUTPUT STAGE

The buffer output stage is comprised of a complimentary emitter follower
configuration of 060 and 061, whose emitter currents are set at approximately 12
mA by bias elements CR62, CR63 and R80.

VOLTAGE GAIN STAGE ONE

The voltage gain input stage consists of a bipolar cascoded differential
amplifier with passive collector loading and constant current source and sink for DC
biasing. 02. 03, R13 and R14 comprise a current sink for total first stage current of
3.2 mA. 600 uA is available to each half of 019, a supermatch pair configured as a
differential common emitter amplifier. The remaining 1.6mA is sourced by Q4. 05,
R12 and R38 for biasingof cascoded common base amplifier 01 by CR1, CR2 and R10,
and 06 by CR3, CR4 and R16.

VOLTAGE GAIN STAGE TWO

The second voltage gain stage is comprised of a differential common emitter
amplifier 09 and 018, cascaded common base amplifiers 010 and 015, with current
mirror 011 and 017, for conversion to single-ended output. Current mirror element
017 is cascaded with 016 as are their circuit complements, 018 with 015, for
isolation from driveline voltage swing. 013 provides bias for 016 and, in conjunction
with CR27 and CR28, for 011 and 017. CR19 provides a constant current load for
013 to ensure that it never turns off.

Second stage current source 012, 014 and R29 provides 57.5mA,
approximately 24mA to each side of the differential amplifier, and the remaining 10
mA through cascade bias chains CR13-CR18 and CR20~CR25 and current sink 07, 08
and R24.

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REGULATOR

Voltage gain stages are powered by regulated + and - 65V supplies. DC
rectification is performed by a discrete full-wave bridge located on the VB-5 PC
board. Two 1900 uF capacitors clamped to the chassis provide filtering before the
unregulated voltages are brought to the channel's two separate, non-tracking
regulators. Since the regulators are complimentary but identical in operation, only
the positive regulator will be described in detail.

A reference voltage is set by 36V Zener diode CR206, and filtered by R207,
0201 and 0203. Zener current is available on power-up through R229 and 0R211; as
regulated output stabilizes. CR211 is reversed biased. CR203 becomes forward
biased, and 0R204 provides a regulated current for Zener operation. A differential
amplifier comprised of 0201 and 0203 compares Zener reference to a portion of
regulator output. Regulator gain {1 + (R225 + R215a)/(R215b + R219)} can be
adjusted by varying R215. Voltage gain is provided by common emitter amplifier
0205, and current gain by emitter followers 0207 and 0209 for the required +65V,
132mA output.

ANTI-THUMP

During turn-on and turn-off, transients are minimized by clamping amplifier
drive lines to ground. Clamping, comparator and timing circuitry is located on the AC-
8 P0 assembly.

1. COMPARATOR

Comparator 0213 monitors -VReg and develops the appropriate voltage across
its collector load resistor, R240, to control clamping action. With 0213's base held to
-12V by CR220, CR222 in Zener breakdown at 47V, and voltage across R244 setting
emitter current, 0213 remains in saturation during normal amplifier operation. If -
VReg falls below the Zener threshold of CR220 + CR222, emitter current through
R244 ceases and voltage across R240 falls to zero.

0214, an N-Channel J-FET. is switched by 0213 to control the voltage at the
junction of R239 and R241. During normal operation, 0214's gate voltage is held at -
12V, well below specified gate-source cutoff voltage. Drain current at this time is
virtually zero. Diode 0R219 is in Zener breakdown and voltage at the junction of R238
and R239 is approximately 12V. When 0213 is not conducting (at turn-on or after
turn-off), 0214's gate voltage fall to 0V, 0214 saturates, and the junction of R238
and R239 is brought to ground.

2. TIMING

0213 will always charge to the voltage at the junction of R239 and R241.
When 0214 is In cutoff (after turn-on and during normal amplifier operation), C213
charges slowly through R239, R241 and R242 to +12V. When 0214 saturates (at
turn-on or after turn-off), 0213 discharges quickly through CR223, R241 and the
drain of 0214 to ground. Charge on 0213 is applied to the gate of MOSFET 0216.