Kenwood TS 940 S Service Manual

Page 1

KENWOOD

TS-9408

SP-940,AT-940.
SO-l,II8-l

HF TBANSGEIVER

CONTENTS
CIRCUIT DESCRIPTION .................... 2 DIGITAL A UNIT (X54-1830-00) ............ 100
SEMICONDUCTOR DATA .................. 35 DIGITAL 8 UNIT (X54-1840~00) (8/2) ........ 100
PARTS LIST ............................ 43 DIGITAL C UNIT (X54-1850-OO) ............ 100
DISASSEMBLY .......................... 62 SW UNIT (P) (J25-3356-04) ---------------- 100
PACKING .............................. 66 SW UNIT (X41-1600-00) .................. 102
ADJUSTMENT .......................... 67 AVR UNIT (X43-1500-00) ................ 102
LEVEL DIAGRAM ........................ 82 DC-DC UNIT (X46-1030-00} ............... 102
TERMINAL FUNCTION .................... 83 RIT ENCODER UNIT (X54-1690-01) ......... 102
PC BOARD VIEWS/CIRCUIT DIAGRAMS MAIN ENCODER ASS'Y {W02-0328-10) ....... 102
RF UNIT (X44-1660~OOI .................. 90 SCHEMATIC DIAGRAM .................... 103
100W FINAL UNIT (X45-1400-00) ........... 90 AT-940 (ANTENNA TUNER] ................ 104
LPF UNIT (X511330-OO) ................. 90 80-1 [STANDARD OSCILLATOR UNIT) ........ 104
IF UNIT (X48-1430-OO) .................. 92 SP-940 (SPEAKER) ....................... 104
CONTROL UNIT (X53-1420-11} ............ 94 VS-1 (VOICE SYNTHESIZER UNIT) ........... 106
PLL UNIT IX50-2020-00) ................. 96 BLOCK DIAGRAM ....................... 107
CAR UNIT (X54-1840-00) IA/ZI ............ 96 SPECIFICATIONS ................ BACK COVER
AT UNIT (X57-1130-00) .................. 98

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TS-9408

CIRCUIT DESCRIPTION

The PLL-1 consists mainly of ICE) 1 MN6147.\/C01 of 012
: 25C2668 is locked in the 100-10999MH7. range. The 1/4
fSTD (BMHZ) signal is supplied from the reference signal
generator to lCQ, where it is divided to 1/500 and output as
a 10l

The VCOl output is applied to the same ICQ via buffer
amplifier 011, where it is divided to l/N'l. The signal is
then coupled to the phase comparator, where it is corn-
pared with the above 10kl-lz signal, and the output locks
PLL-1 in 10kHz steps.

As N1, the 1000 steps (10000-10999) of dividing data
equivalent to the low order 9.99kHz width of the operating
frequency is sent from the digital A unit to the PLL unit as
a 4 bit serial data stream. A microprocessor is used for this
data sending operation. lDAO-DA3, CKl) In FSK mode, as
the space frequency is used as an operating frequency, N1 is
shifted to 10229~1 1228.

The PLL~1 output is divided to 1/100 by |C10; M54459L
and becomes a signal of 1MHz-1.0999MHZ (1.0229-
1.12281vll-lz in FSK mode) in 100l-lz steps. This signal sent
from the PLL-i channel to |C6 : SN16913P, i.e., the signal
sent from the PLL-1 channel to ICES is:

N1 1 N1

{Ch-1- - -- <- '~- .. .- . i 'i
100-100X500X4 f"-"200000 f ~12

On the other hand, the fVC04 + fVCOE} signal (approx.
117MH7) is sent from the carrier unit to PLL unit. This
signal is divided to 1/10 by IC5 : HDlObSl and applied to
the mixer |C6. This signal is expressed by the equation :

l i

10 - (f'-.icev-i+f'-.ica?=)=1o

{100 - fcstti -i- l 00 (é-fs i c -f-;:i'-.H2 )ll

=5.fs~0+10fcml_ioma2 ............... .123

it becomes a signal of approx. 11 7Ml-lz. Therefore, lC6
output becomes a signal of approx, 10.65MH2 expressed

by:

5fstE-+1Ofc:t-u~10fcria2-20%6 'fsr3 """""""""""""" (Si

Any mixer spurious is eliminated by ceramic filter CF1 :
SFJlOJMA-D and applied to the next PLL-2 loop. PLL-2
consists mainly of ICB ; MN6147, which locks the output
signal of mixer |C7 : SN16913P, which is the VC02 output
of Q7 : 28C2668 and the signal front CFl, in the range of
46.2-51.1MH2. The 1/2 fSTD 110MHz) signal is supplied
from the reference frequency generator to lC8, where it is
divided to 1/500 to make a Comparison frequency of 20
kHz. The VCOZ output is applied to mixer |C7 via buffer
amplifier 06 : 2SC2668 and added to the signal (the con-
figuration of equaion (3) =2 10.65MHz] from CH, and this
output is sent to ICB via a BPF (Band Pass Filter) and amp-
lifier 010 : 2SC2668.

This signal is divided to 1/N2, compared in phase with the
above 20kHz signal and used to control VCOZ This ope-
raiton is expressed by :

N1 4, .)
200000 T

_l___1_ 1 . . ......... ii
X N2 -500X2f$l.. l4}

(fveez +5fsto+10fcnR1-10fcnn9-

N2 means to cover the low order 500kl-lz width of the
operating frequency in 10kHz steps and takes a numeric
value of 50 steps which beocmes an integer multiple of 5 in
the range 2310-2555. Like Ni in PLL-1. this data is sent
by the microproceesor from the digital A unit to the PLL
unit |C8 as a 4 bit serial data stream. (DAO-DA3, CK2)
Therefore, the output signal of PLL-2 is expressed by the
equation :

....- N E _ m- ................ H
fuLJz- (200000+ 1000 5) f): L 1Of'..:-.H1+1Oft.nl{4 t5}

According to the values of N1 and N2, a frequency of
35.5-40.4999MH2 is generated in 1001-12 steps. The PLL-2
output is divided to 1/10 by lCl'l 7 H010551 via buffer
amplifier 015 : 2SC2668, and becomes a signal in 10Hz
steps in the 3 55-4.04999MH/. range.

First, iSTD (20MHzl is added in mixer |C12 : SN16913P
and then, 3.fSTD (BOMHzl is added in mixer |C13 :
SN16913P and the signal is converted to 8355-8404999
MHz. As a result, 4.fSTD (BOMHzl is added, but such a fre-
quency configuration is employed in order to avoid un-
wanted mixer spurious components. This signal is applied
to mixer |C14, where it is mixed with the final VCO output
signal.

Item Flatlng

Center frequency D : 10.64MH7t30k H7 (Black)

280i50kHz within
_ _ 750kHZ or less
7:2dB within

:3dB band width
50dB bandwidth

Insertion loss
(i,

Spurious attenuation

_a

5598 or more at 9-13MH2
Input and output impedance 330.9.

-r

Table 3 PLL ceramic filter (L72c0349-04l (PLL unit CF1)