Kenwood DSP 100 Service Manual

Page 2

USP-100

CIRCUIT DESCRIPTION

Overview of the DSP-100
1. Functions
The USP-100 performs digital signal processing for
the following:
583 modulation
CW
AM
FSK modulation
Carrier generation during freQUency modulation
PSN detection and audiofrequency low-pass filter-
mg
088 detection and audio-frequency low-pass filter-
ing

2. DSP-IOO Foetum
- Modulation method

The USP-100 has the same performance as the
DSP~10, and carries out $88 modulation by the PSN
method. CW waveform shaping with a ROM filter, and
waveform shaping with a FIR filter to speed up FSK.
The DEF-100 has Gaussian characteristics to reduce
CW and FSK distortion.

- Demoduletlon method

The signals on both sides of the carrier point are
detected for 858. CW. and FSK demodulation by the
conventional product detection method. 0n the other
hand. the PSN detection method detects only one side
band by controlling the phase. and so achieves sharp
and superior side-band suppression characteristics and
low group delay distortion. like a very sharp filter.

3. Configuration

Figure 1 is a block diagram of the DSP. The 03?
consists of a digital unit, which controls operations and
carries out digital signal processing: an analog unit,
which processes analog signals, outputs them to the
digital unit, and converts the signals from the digital
unit to analog signals: DDS unit, which generates a
zero input limit cycle suppression signal. and a PLL
unit. which generates clocks for executing centralized
management with external reference signals and for
carrying out digital signal processing with an accurate
sampling frequency.

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Page 7

DSP-100

CIRCUIT DESCRIPTION

- Switch input

The front panel switches Output ST 0. 5T1, and 8T2
strobe signals to $1. $2. and 83/84/85, and read the
returned RTO to RT6 to determine the switch status.
Ten DIP switches on the rear panel are directly con-
nected to the microprocessor.

. TXB. BBC

The remote transmission/reception mode is set by
the transceiver. and the microprocessor changes be-
tween transmission and reception according to the
T'XB level. For quick change for full break-in in CW
mode. the DSP checks TXB and changes between
modulation and demodulation. The DBC is a DSP con-
nect signal that goes low regardless of the TX/RX on/
offswitchMiletheDSPis operating. WhenthePLLis
unlocked. the signal goes high to stop DSP operation.

2) DSP

The DSP is a high-speed processor for digital signal
processing that uses a 25MHz crystal for internal clock.
ing and operates with 6.25MHz l160ns) clocks (1/4 the
25MHz signal). Most instructions. such as addition (16
+ 16 bits) and multiplication (32 + 32 bits). are carried
out in one machine cycle. The DSP contains a #Kword
EPROM and a 256word RAM.

It interfaces with the analog-to-digital and digital-to-
analog converters. receives commands from the main
unit, and reads switches through the gate array con-
nected to the bus.

- Gate array

Functions such as generation of internal/external
clocks from the PLL internal reference signal: analog
unit interfacing: and DSP reset signal generation. corn-
mend transfer from the microprocessor to the DSP.
and RTK, CKY. and TXB input are implemented on a
single chip to reduce the size of the (figital unit circuits
and increase reliability. Analog control lines M00 and
IFE are controlled by the DSP via the output port of the
gate array to increase the flexibility in changing the
specifications of the DSP program.

- Otinr DSP peripheral components

)0 provides timing for writing chta to the gate ar-
ray. |C42 is a power detection IC that outputs a low
signal to the gate array if the power supply voltage
drops. When the power is switched on. the output
from this IC is directed to the DSP with a delay by the
gate array. 027 is an amplifier that amplifies the DSP
reference signal to the gate array input level.

2-3. Analog Unit

The analog unit interfaces the transceiver and digital
signal processing units. including the analog-to-digital
and digital-to-arialog converters.

1) High-peas liter

The high-pass filter for sound quality adjustment
(bandwidth limiting) is not an analog filter. but a digital
filter for modulation that makes use of the processing
capability of the DSP. and the same characteristics are
used for both modulation and demodulation. The char-
acteristics are those of a fourth-order Butterworth fil-
ter. and the cutoff frequency (-8 dB) can be obtained
by the following formula:

Fc s mar-sort (Ra-Rb-Ca-Cbl (Ca = Cb)

The cutoff frequency of the high-pass filter can be
changed in four steps by changing the resistors with
analog switches. The high-pass filter switch position is
set to the cutoff frequency for the overall characteris-
tics for the notch filter and high-pass filter for $58
modulation. The cutoff frequency of the high-pass fil-
ter is used when the notch filter is off. during ampli-
tude modulation and demodulation.

Position THPo HP1 HPFcutoff frequency
100 l 1 5H:
200 o 1 1:3st
300 1 o 300Hz
400 o o 1 40on

Tablei High-passiltercutofffrequency

2) Limiting amplifier

if a signal whose amplitude is higher than the ana-
log-to-digital converter input amplitude is input to that
converter. a Very large distortion occurs. To prevent
this. the amplitude is limited with a limiting amplifier
so that it does not exceed the full scale of the analog-
to-digital converter input. This is done by clipping the
amplitude with a limiting amplifier. The limiting ampli-
fier is an operational amplifier in the HIC. and the ampli-
tude is clipped by IC12 when it exceeds 11.6 V.

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USP-100

16

CIRCUIT DESCRIPTION

lc Operation
Ph mm. Pin [[0 Signal Function Condition (or HIL Romulus
. norm bolnLoctivo
P87-P34 62~65 Unused
P83 66 0 DEC 05? presemelabsenco signal
982 I 67 I SMOD T3950 mode selection 75-950 mode L
P81 68 I UNLK UnIock sugnal ' Urfiock H I
P80 69 I TXB I Transmivrecoivo dungeon! sign! 1 TX L '
Vss 70
o 71 0
MP1 72 I CPU opomnon mode determination Fund L sinoIe chip mode
MPO 73 I I ' L
XTAL 74 I I
EXTAL 75 I
Va: 2 76 I
PE7-PES ; 77-79 0 I Unused
FESH' 1a) :1 J

- Pulse waveform design
Timing from the microprocessor to PLL and DSP

Data x

X _

30113 64113
Clock
I musi 32us 26ps
Enable FI-
Koy soon timing
20ps
Key scan I
PD 4:19 _J L-J
20%
Kayscan
PD 5:20

3725.15
Key wan
PD 6:21