Jvc BR SAR200 E Service Manual Part 5

Page 29

7.3 VIDEO CIRCUIT

1. VITO MIX circuit

When the TIME CODE board is incorporated in the VTR. this
circuit mixes VITC (Vertical Interval Time Code) signal in the
V. blanking period. One line comprises of 90 bits and the
signal is mixed in two lines of the 19H and 21H lines in the
initial setting mode.

2. AUTO E0 MIX circuit

This circuit mixes reference signal supplied from the AUTO
EQ board. In the initial setting, reference signal is mixed in
11 lines only in the S-VHS mode.

0 Outline of AUTO E0 circuit

The AUTO E0 circuit is installed to prevent frequency re-
sponse from deterioration caused by demagnetization of tape
and to control irregularity in respective frequency character-
istics of tapes used. Two reference signals of 625 kHz and
3.8 MHz are recorded in optional lines in the V. blanking pe-
riod. and the video equalizer is controlled in playback to
equalize PB level of each reference signal with that of the
original. Accordingly. the frequency response is automatically
adjusted in the S-VHS mode.

This VTR is designed to be used as a recorder, therefore, it
adds reference signal but has not equipped with any auto-
matic PB adjusting circuit. in case of the BR-SSZZE, it gets
AUTO E0 reference signal blank in video output, however,
the BR-S422E does not blank the reference signal and out-
puts it as it is added.

0 Reference signal generator circuit

Reference signals are generated by the gate array IC (IC1,
JCLOOOS). This IC receives 4 fsc clock through the pin @
while it receives sync. signal through the pin @, and it out-
puts 625 kHz reference signal through the pin ® while
3.8 MHz reference signal through the pin ()2). These refer-
ence signals are supplied to the LPF and BPF circuits which
mix them to be output as the reference signal synchronizing
with the sync. signal.

Pins CD, @ and (5) function to control the reference signal in-
sertion line which is selected by SW1. In detail, line selec-
tion is performed by SW1-2, SW1 -3 and SW14, and. when
all of them are on, nothing is selectd for insertion. If SW1 -1
is off. the SW 5V signal line of the circuit is cut off, therefore
insertion is not activated without change of the insertion lines
set by SW1-2. -3 and 4.

R29 and R38 are variable resistors to adjust reference signal
level so that the ratio between sync. level, 3.8 MHz level and
625 kHz level becomes 4 : 2.0 : 4.0 since this VTR has not
the playback circuit for automatic level adjustment. (For a
reference, the BR-SSZZE records sweep signal and plays it
back to obtain the specific frequency response.) The above-
mentioned ratio is determined to obtain the specific frequency
response on the condition that the BR-S422E is used for re«
cording and the BR-SBZZE for playback.

«:2 [c3 rcr JCL0009 LPF R29
l 625 kHl TP1
m x4 >- 6 cm nszra-E- - ©
9 ' src our
3.3 MHz 3"
m Esta-E?
3.3 MHZ 625 kHz
R38
even
3 L50
4 L51
1-4
0- 5 L52
Flg. 7-3-1

Page 40

7.5.2 Mode shift

The control cam changes its position appropriately for
shifting the component pans so that they works to meet
the selected mode.

Symbol No. Mode Details of Mode
1 EJECT Ejection (to take out cassette)
2 FF/REW FF (Fast Forward), REW (Rewind), Short FF

Loading, Unloading

PLAYBACK Playback, Still, Shuttle Search (+), REC (Recording), INSERT (Insertion), After-recording
BACK SPACE Back spacing

PAUSE Pause

REVERSE REV (Reverse), Shuttle Search (-), Preroll

i
I
l
3 : STOP Stop, Short REW
I
I
I
I
|
I
|

-t : in the Loading direction
- -> : in the Unloading direction
Table 7-5-1 Mode shift

1. Stop mode (Symbol No. 3)

1. In this mode, the main brake is in close contact with the 3. Both the FF brake and REW brake are in contact with
clutch to prevent the tape from slackening in the cassette. the reel disk.
2. The take-up idler is fixed at the neutral position by func- 4. The search brake is off the reel disk by function of the
tion of the cam (3). cam (1). (Fig. 7-5-5)
Cam (3) _, Slide plate-> Relay lever» TU idler _] 5. The pinch roller is positioned considerably apart from

the capstan by function of the cam (2). (Fig. 7-5-6)

Capstan motor
Pinch roller
Cam (3), Control cam Capstan
FF brake

Lt Control plate

Cam lever (3)

Take~up reel disk

Search brake

Relay lever _ Take-up idler
Ma'" brake Control plate
Take-up clutch

Supply clutch

Fig. 7-5-4 Stop mode

7-22

Page 52

- Serial input signal

Each port of pins@ to@of ICI time code generator is
supplied with 8-bit serial signal which is generated by
converting parallel signal into serial signal by the multiplexers
of IC7 to IC10. At that time. the multiplexers are controlled
by L880. L800 and LSDO outputs from pins®to® of

IC1.

Table 7-82 shows four serial signals generated by the above

process.

+5v ICIO MPX lCl TCG

Fig. 7-6-4 Parallel-serial converter circuit

Pin Signal Description
No. Name 0 I I I 2 I 3 I 4 l 5 6 I 7 L
I I I I , I I I
I I
13 sex 0 I I I I I I I I I I
I I I I I I I
l : I I I l l I
l I I | I l 4
I9 L53 0 I I I I I I I_
I l I I .
-I"°»"II" I I I I i I
I I I
20 Lsc o i I I__,_I: i I-
I I I I I I
i i I I i I I
I I I I I
2r LSD o i I I I I I
I I . I I
. I . I
Tcma us/nr mun/:11. RT ua RESEY man an
'4 OFF RUN 0
22 PORTA DIPSW)
3-1
L ua 'Iffié CTL on 1.1:: on HOLD 0N
SLAVE sSELo SSELI SLEB ERCLR DLODI 01.002 VITc
, DATA DATA
n OFF RESET 2 OFF w m EI
23 PORTS 1 j m
L on SET SET 8 on c (3 52
AS I as 2 A83 A54 ass ASS A57 ass
M RESET RESET RESET RESET 4FIELD 7:55,?
2 ""c (CF) Ian)
I. sET SET SET sET SET SET
szA swan swu swu Svlll swza swzc swap
SWIA/SWIILHLHLNLMLMLHLHLH
25 RT WELLHHLLHHLLHNLLNH
swwswamLLLLnnnuLLLLMHHM
WWLLLLLLLLHHHHHHHH
worm
LINE m. 22212019181716151413121110 9 a 7

Note 1: In the above table, indications in the box are always fixed in those conditions.
Note 2: Port C controls on/off of assinged bits. A81 to A86 are assigned to the following bits.
LTC VITC Remark
A51 10 14 Unassigned Bit
A82 11 15 Color-lock Flag Bit
A53 59 75 LTC Bi-phase Mark Phase Correction Bit or VITC Field Mark Bit
(Settable by DIP switch SW3-1 on the DISPLAY board)
A54 27 35 Binary Group Flag Bit
A85 58 74 UNASSIGNED ADDRESS BIT
A56 43 55 Binary Group Flag Bit

7-34

Table 7-6-2