Heathkit IB 1100 Manual

Page 2

Page 30

Detail 2-7A

_HlATI-IKIT®

FINAL ASSEMBLY

CHASSIS

PICTORIAL 2-7

Refer to Pictorial 2-7 for the following steps.

(VI' Refer to Detail 2-7A and remove the five 6-32 x 5/16"
screws which hold the circuit board to the chassis at
AP, AR, AS, AT, and AU. Do not remove the screw at
AG.

(Vlr Refer to Pictorial 2-7 and slide the chassis into the
cabinet shell.

(VI Install six #6 x 3/8" sheet metal screws through the
cabinet shell and into the rear panel at BG, BH, BJ,
BK, BL, and EN.

(vi Refer to Detail 273 and install 6-32 x 5/16" screws
through the cabinet shell, chassis, and into the circuit
board spacers at AP, AR, AS, AT, and AU.

(u)/ Install a #6 x 3/8" sheet metal screw through the
cabinet shell and into the chassis at AN.

This completes the assembly of your Frequency Counter.
Proceed to the "Calibration section.

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Page 31

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Detail 2-7B

CALIBRATION

This section of the Manual contains two calibration
procedures. If you have access to a reliable frequency
counter and/or an accurate frequency generator, proceed to
the With Instmments" procedures on Page 34. If these
instruments are not available, proceed with the following
Without Instruments procedure.

The accuracy of your Counter depends to a great extent
upon the care and accuracy that you exercise in performing
the following steps. If at any time you do not obtain the
results called for in a step, refer to the "In Case of
Difficulty section on Page 36 to correct the problem.

Without Instruments

IMPORTANT: Most communications receivers and standard
(AM) broadcast receivers, especially those with a built-in
antenna coil, have sufficient sensitivity to produce the
audible difference frequency called for in the following steps
with the cabinet shell remaining on your Counter. However,
if you are unable to hear the difference frequency, try
another receiver and/or remove the cabinet shell from your
Counter before you assume there is a difficulty.

( ) Turn the Counter on and allow it to warm up for 30
minutes. This is MOST IMPORTANT for an accurate
calibration.

( l Push the RANGE switch to the MHz position.

( ) Remove the test cable from the counter INPUT
connector, if it is not already done.

Page 4

Page 34

HEATHKITe

With Instruments

The accuracy of your Counter depends to a great extent
upon the care and accuracy that you exercise in performing
the following steps. These steps are designed to be used with
precision equipment to calibrate the clock and the input
sensitivity of your Counter. If at any time you do not obtain
the results calledfor in a step, refer to the "In Case of
Difficulty" section on Page 36 to correct the problem.

NOTE: In the following steps, the cabinet shell should
remain on the Counter.

(\/) Turn the Counter on and allow it to warm up for 30
minutes. This is MOST IMPORTANT for an accurate
calibration.

INPUT SENSITIVITY

This adjustment requires the use of a signal generator with a
continuously variable output from 25 mV to 0.5 volt rms,
capable of generating at least a 1 MHz signal.

Refer to Figure 3-3 (fold-out from Page 30) for the
following steps.

(VT 1. Connect the test cable to the INPUT connector of
the Counter.

(VT 2. Connect the Counter test cable to the output of the
signal generator.

(/) 3. Select a frequency between 1 MHz and 30 MHz.
Set the signal generator output voltage to
approximately 0.5 volt rms.

(J) 4. If the Counter does not indicate this frequency, use
your white alignment tool and adjust the INPUT
COARSE control (see Figure 3-2 on Page 33) until
the correct frequency is displayed.

(VI/5. Reduce the signal generator output voltage until
the display becomes unstable or goes to zero.

(V) 6. Slowly readjust the INPUT COARSE control to
again obtain a correct display.

(A 7. Repeat steps 5 and 6 until you reach the smallest
signal generator output voltage that still produces a
correct display on the Counter.

(W) 8. Repeat steps 5, 6, and 7 using the INPUT FINE
control.

NOTE: The TP LEVEL control is used only to vary the
signal level at the TP OUTPUT during the "Calibration
Without Instruments."

CLOCK

This calibration can be performed with either a frequency
counter and a signal generator (capable of a 1-30 MHz, 250
mV output) or with a known, stable, laboratory standard
frequency. Determine which of these methods you will use.
Then complete the steps under the appropriate heading.

Calibration With a Frequency Counter and
Signal Generator

Refer to Figure 3-4 (fold-out from Page 30) for the
following steps.

NOTE: The accuracy of your Counter, for this type of
calibration, is dependent on the accuracy of the test
frequency counter.

( V) Connect the test leads of the test frequency counter to
the output terminals of the signal generator.

(/l Also connect the test leads of your Counter to the
output terminals of the signal generator.

(\/{ Press the RANGE switch to the kHz position for
maximum resolution.

( ) Set the signal generator to any convenient freqency
between 1 MHz and 30 MHz at 250 mV to 500 mV
output.

( ) Use the white alignment tool and adjust the TIME
BASE OSC capacitor (see the inset drawing on Figure
3-4, fold-out from Page 30) until your Counter
indicates exactly the same frequency as the test
frequency counter.

( ) Disconnect the test leads.

This completes the calibration of your Frequency Counter.
Proceed to the Operation section .

Calibration With a Known Laboratory
Standard Frequency

NOTE: It is essential that the known frequency source
(frequency of your choice between 1~30 MHZ) be absolutely
stable. The accuracy of this type of calibration ls entirely
dependent on the accuracy of this known frequency.

_I-IEI.ATHKITE'

I ) Connect the known frequency to the test cable of the
Counter.

( ) Push the RANGE switch to the kHz position for
maximum resolution. NOTE: If the frequency is 100
kHz or higher, the overrange lamp will be lighted.

Page 35

( ) Use the white alignment tool and adjust the TIME
BASE OSC capacitor until the known frequency is
exactly indicated on your Counter.

This completes the calibration of your Frequency Counter.
Proceed to the "Operation" section .

OPERATION

Refer to Figure 3-5 (fold-out from Page 41) for a description
of the display, control, and adjustment functions.

CAUTION: Use ONLY the center conductor of the input
lead of your Counter to check the frequency of an ac line
voltage. Connecting the ground input lead to the hot"
(ungrounded) side of an ac line may result in a blown fuse
and/or damage to your Counter.

CONTROLS

This Frequency Counter has only two controls: the Power
ON/OFF switch and the MHz/kHz Time Base switch. The
Time Base switch selects a 1 millisecond time base in the
MHz position, or a 1 second time base in the kHz position.

INPUT PROBES AND CABLES

Any standard 10 megohm oscilloscope probe can be used
with this Counter. Refer to the Maximum Input Voltage for
the maximum AC voltage that can be applied to the INPUT
of the Counter at various frequencies. Note that even though
the input of the Counter is AC coupled, the DC input level is
limited to 200 volts.

When you connect your Counter to a transmission line,
make sure that the line is properly terminated (low standing
wave ratio) to avoid possible damage to the equipment
under test.

READING THE COUNTER

CAUTION: Avoid any excessive voltages that could damage
your Counter. Refer to the Maximum Input Voltage for
maximum safe input voltages at various frequencies.

Maximum Input Voltage

Up to a frequency of 10 kHz, the maximum permissible
input voltage is 150 volts rms. At frequencies above 100
kHz, the maximum input voltage must be derated according
to the following graph.

200
175
150
125
100

75

50

25 24. 7v

IOMHZ
30MHZ

MAXIMUM INPUT VOLTAGE DERATING CURVE

IHZ IOHZ IDkHZ IODKHZ IMHZ

Unknown Frequencies

To measure an unknown frequency, push the Power switch
to ON and the Range switch to kHz. Allow the Counter to
reset to zero. Then apply the unknown frequency to the
counter input. If the OVER (overrange) lamp lights up, the
frequency is higher than 99.999 kHz and the Range switch
should be pushed to MHz. If the display then constantly
changes in a random manner, the frequency is higher than
the Counters capability, or the input level is too low.

The Display

Frequencies lower than 100 kHz can be read directly to a
resolution of :1 Hz in the kHz position of the Range
switch. Frequencies of 100 kHz and higher (within the range
of the Counter) can be read to 11 Hz by using both Range
switch positions. A frequency of 12,345,678 Hz would be
displayed as follows:

Range Overrange
Switch Display Lamp
MHz 12.345 Off

kHz 45.678 On

Page 8

Page 42

_I-IEA.THKIT@

CIRCUIT DESCRIPTION

Refer to the Block Diagram (fold-out from Page 45) and to
the Schematic Diagram (fold-out from Page 55) while you
read this Circuit Description.

GENERAL

Your Heathkit Frequency Counter includes a 1 MHz clock
and scalar that produces an exact time base of 1 second or 1
millisecond. This time base controls all of the gating circuits
and determines the overall accuracy of the Counter.

The output of this clock and scaler circuit is applied to the
reset, gate, and memory circuits to reset the counters, gate
the first decade counter for a precise period, and to transfer
the count to the decoder and display tubes.

The input amplifier and Schmitt trigger circuits accept and
shape the input signal into a squarewave, and then apply this
signal to the first decade counter. When this counter is
turned on, the pulses from the input and shaper circuits are
counted in BCD (Binary-Coded-Decimal) logic, with each
tenth pulse passing to the next decade counter. The outputs
of the decade counters are in the 1-24-8 or "natural" binary
code.

When the transfer pulse is applied to the memory latches,
they accept the accumulated BCD count from the decade
counters and hold this count at their outputs until the next
transfer pulse. The outputs are connected to the
decoder/drivers, which translate the 800 count into a
decimal count and turn on the proper numbers in the
display tubes. Any tenth pulse from the fifth decade counter
triggers the overrange detector and readout circuit to cause
the overrange (Over) lamp to light. The reset pulse occurs
after the transfer pulse and resets the counters to zero for
the next counting cycle.

INPUT CIRCUIT

The input circuit consists of a network of capacitors,
resistors, transistors, and diodes that function as follows: C1
removes any do component from the applied input signal.
C2 prevents attenuation of high frequency signals, and R2,
D1, and D2 prevent overloading of the input transistors.

input transistors 01 and 02 are direct coupled with 100%
negative feedback. These transistors provide wide band-
width, high input impedance, low output impedance, and a
gain of near unity.

Transistor 03 is an amplifier with emitter compensation,
and is isolated from the Schmitt trigger circuit by the
emitter-follower configuration of transistor 04.

SCHMITT TRIGGER

The Schmitt trigger circuit is a regenerative bistable circuit
which produces a square-wave output each time it is
triggered and reset. Schmitt trigger transistors 05 and 06 are
emitter-coupled for current-mode operation so they will
produce the fast switching time required for operation of
the first decade counter. Operating current for the trigger is
set by resistor R13, while R15 sets the bias of zener diode
ZD1 in its zener region.

Input Sensitivity controls R3 and R6, by virtue of do
coupling, adjust the threshold of the Schmitt trigger circuit
to insure that very small input signals can be measured with
the counter.

Emitter follower transistor 07 keeps the TTL
(transistor-transistor-logic) in the counter circuit from
loading the Schmitt trigger circuit.

1MHz CLOCK AND SCALER

A 1 MHZ crystal and gates A and D of |C21 are used to form
a TTL - compatible clock. Capacitors CB and 011 provide
the proper capacitive load for the crystal. 011 is variable to
allow for precise calibration of the oscillator. Resistors R28.
R29, and R31 assure efficient starting of the clock
oscillator. Gate B of lC21 provides buffering action between
the oscillator and the first decade divider of the time base
scaler.

The scaler consists of six decade dividers. The Range switch
selects the output from the third or sixth divider for the
reset pulse, and either the A output of lC18 or the 0 output
of lC24A for the input gating pulse. Therefore, the Range
switch can provide either a 1-millisecond (MHz) or a
1-second (kHz) time base for the gating, reset, and memory
circuits. The A output of |C20 provides the transfer pulse.

GATING, MEMORY, AND RESET

The gating, memory, and reset circuit controls the times that
an input signal is gated into the counting circuits, the times
that the accumulated information is passed from the
counting circuits to the readout circuits, and the times that
the counter circuits are reset to zero to begin a new counting
cycle.

Page 43

Figure 4-1 (fold-out from Page 42) shows the pulse
relationships of the gating, memory, and reset circuit. Refer
to this Figure as you read the following information.

When the Range switch is in the MHz position, the gate
open" signal is a 1-millisecond pulse that is obtained from
the A output (pin 12) of |018. The input signal enters the
counters during the millisecond that the logic 1 of the gating
signal is present on the J and K inputs of the first flip-flop of
the first decade divider (pins 9 and 3 of |C25).

The reset pulse is derived by combining the inverted gate
signal with the output of |C17 in ICZSD. During the time
that both the output of |C17 and the inverted gate signal
from |C23C are high, a logic 1 at both inputs of NAND gate
IC23D causes a logic 0 reset pulse to be applied to the first
DCU (decade counting unit) and to lC24B, the overrange
flip-flop. This reset pulse is inverted by 08 to supply a logic
1 reset pulse to lC's 11 through 14. These reset pulses occur
every two milliseconds, immediately prior to the gate
opening.

The transfer signal is derived by combining the reset pulse
(pin 11 of |C23D) with the inverted gate pulse in NAND
gate lC23A. The resultant pulse is then inverted by l021C.

A transfer pulse cannot occur during a reset pulse because
ICZSB is inhibited by a logic 0 on its pin 4 from lC21C. The
transfer pulse can occur only when pin 4 is at a logic 1 and
during a postive-going transition at the A output of |020,
which is differentiated by 012 and R36 and applied to
[023B as a positive spike. [0238 then has a logic 1 at each
input and therefore a logic 0 output. The negative output
spike is inverted by 09 and the positive spike is applied as a
transfer pulse to lC's 6 through 10, and lCs 22A and 220.

Although the reset cycle occurs every two milliseconds, the
differentiated A output of |C20 allows the transfer pulse to
occur only every 200 milliseconds. Therefore, 100
count-reset cycles will occur for every memory update to
prevent the appearance (due to the persistence of the human
eye) of more than one lighted number in the last digit.

When the Range switch is in the kHz position, the gate
open" signal is a 1-second pulse that is obtained from the 0.
output (pin 12) of lC24A.

The reset pulse is derived in the same manner as with the
Range switch in the MHz position, except that the basic
signals are obtained from the 0 output (pin 11) of ICZO and
the 0 output of |C24A.

The transfer pulse is also derived in the same manner as with
the Range switch in the MHz position, except that the gate
reset cycle now occurs every two seconds and the transfer
occurs every 200 milliseconds (unless inhibited by the
presence of either a reset pulse or a gate-open pulse).
Therefore, there are four transfer pulses for every gate reset
cycle. These extra pulses, however, will have no effect on
the readout since neither the gate-open nor reset can
occur during their time duration. As a consequence, the
same count is simply transferredfour times.

FIRST DECADE COUNTER

Figure 4-2 (fo|d~out from Page 42) shows the pulse
relationships in the first decade counter (l625, lC26A,
ICZSB, |C27). Refer to this Figure as you read the following
information. '

This circuit is connected as an asynchronous BCD counter,
and the flip-flops are triggered by negative-going pulses.
Flip-flop |C25 is toggled by the signal from the Schmitt
trigger circuit. As l025 is toggled on every input pulse when
both the J and Kinputs are at logic 1, the (1 output (A) .goes
to a logic 1 on the 1st, 3rd, 5th, 7111, and 9th counts.

These pulses are then applied to the toggle input of |C26A.
However, because of the feedback loop from O of |027 to
the J input of |C26A, lC26A is inhibited on the tenth count.
This results in the 0 output of |026A being a logic 1 for the
2nd, 3rd, 6th, and 71h counts. lC2SB is toggled by the 0
output of |C26A on the 4th and 8th counts. Therefore, the
0 output of |C2GB is a logic 1 for the 4th, 5th, 6th, and 7th
counts.

Two feed-fontvard loops are incorporated around |CZ7,
which is toggled by the 0 output of lC25, to inhibit its
toggling on any pulse except the 81h and the 10th count.
This is accomplished by connecting the 0 outputs of |C26A
and ICZBB to the J inputs of lC27. As a result, lC27 will
toggle only when both of the 0 outputs from |C26A and
|C2BB are at logic 1. This results in the 0 output of l027
being at logic 1 for the 8th and 9th counts only. On the
10th count, lC25 toggles to a logic 0 at its 0 output as its J
input is a logic 0. ICZGA and |C26B will stay at logic 0 as
they were not toggled. |C27 is forced to logic 0 because its J
input is at logic 0.

Reset is accomplished by taking all clear inputs of the
flip-flops to a logic 0. These logic levels are supplied by
ICZSD. Counting is started when the J and K inputs of lC25
are taken to logic 1, and inhibited when these same inputs
are returned to a logic 0. These logic levels are supplied by
the A output of |C18 or the 0 output of |C24A, as
determined by the position of the Range switch.