Denon DN D6000 Service Manual

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I DN-D6000 I

3. Mecha unit
(1) Remove 8 screws 59.
(2) Disconnect FFC cable.
(3) Remove 2 screws 51 and 2 screws 53
(4) Detach Mecha unit.

Mecha unit

Note:
0 Do not pull out aslant to prevent Flat cable damage.
0 Do not fail to pull AC cord from wall outlet before disconnect the Flat Cable.
If AC cord is remained plugged into wall outlet, power is kept supplied in the unit, which may cause danger

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I DN-DBOOO I

5': Pin Name Symbol IIO DET Ext Ini Res Function

40 GND GND - - - - - GND

41 GND GND - - - - - GND

42 GND GND - - - - - GND

43 GND GND - - - - - GND

44 GND GND - - - - - GND

45 VDDEXT VDDEXT I - - - - |/O power supply (+3.3V)

46 PF5 DSPF3 O - - L - Programmable flag 5, Flag 3 to pcom (RESERVE)
47 PF4 DSPF2 O - - L - Programmable flag 4, Flag 2 to pcom (RESERVE)
48 PF3 DSPF1 O - - L - Programmable flag 3. Flag 1 to pcom (RESERVE)
49 PF2 DSPFO O - - L - Programmable flag 2, Flag 0 to pcom (RESERVE)
50 PF1 DTIME O - - L - Programmable flag 1. Clock for playback output

51 PFO BTEND O - Pd L L Programmable flag 0. All and : H

52 VDDINT VDDINT | - - - - Core power supply (+1.2V)

53 SCK O - - L - Master slave clock

54 MISO O - - L - Master in slave out

55 MOSI O - - L - Master out slave in

56 GND GND - - - - - GND

57 VDDEXT VDDEXT | - - - - l/O power supply (+3.3V)

58 DT1SEC O - - L - Playback data send 1

59 DT1PR| DDATA I - - - - Digital out data send 0 (serial port OUT 1)

60 TFS1 DLRCK I - IPu - H Digital out send frame sync (LRCK) signal (serial port OUT 1)
61 TSCLK1 DBCK | - - - - Digital out send frame sync (BCK) signal (serial port OUT 1)
62 DR1 SEC | - - L L Playback data receive 1

63 DR1PR| | - - L L Playback data receive 0

64 RFS1 O - - L - Receive frame sync (LRCK) signal (serial port IN 1)
65 RSCLK1 O - - L ~ Receive frame sync (BCK) signal (serial port IN 1)
66 VDDINT VDDINT I - - - - Core power supply (+1.2V)

67 DTOSEC O - - L - Playback data send 1

68 DTOPRI ADATA | - - - - Analog playback data send 0 (serial port OUT 0)
69 TFSO ALRCK | - lPu - H Analog playback send frame sync (LRCK) signal (serial port OUT 0)
70 GND GND - - - - ~ GND

71 VDDEXT VDDEXT I - - - - |/O power supply (+3.3V)

72 TSCLKO ABCK I - - - - Analog playback send frame sync (BCK) signal (serial port OUT 0)
73 DROSEC | - - L L Playback data receive 1

74 DROPRI SRDATA | - - - - Playback data receive 0 (serial port IN 0)

75 RFSO LRCK O - - - - Receive frame sync (LRCK) signal (serial port IN 0)
76 RSCLKO BCLK | - lPu - H Receive frame sync (BC K) signal (serial port IN 0)
77 TMR2 O - - L - Timer 2

78 TMR1 O - - L - Timer 1

79 TMRO O - - L - Timer 0

30 VDDINT VDDINT | - - - - Core power supply (+1.2V)

81 TX TX 0 - - H - UART send

82 RX RX | - Pu - H UART receive

83 _EMU _EMU O - - - - Emulation status

34 _TRST _TRST I - Pd - L Test reset (JTAG)

35 TMS TMS | - Pu - H Test mode select (JTAG)

36 TDI TDI | - Pu - H Test data input (JTAG)

87 TDO TDO O - - - - Test data output (JTAG)

88 GND GND - - - - - GND

89 GND GND - - - - - GND

90 GND GND - - - - - GND

91 GND GND - - - - ~ GND

92 GND GND - - - - - GND

93 VDDEXT VDDEXT I - - - - I/O power supply (+3.3V)

94 TCK TCK I - Pu - H Test clock (JTAG)

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