BOSS DE 200 SERVICE NOTES

Page 2

DE-200

CIRCUIT DESCRIPTIONS

The flow of delay signal through the DE-200 is outlined in the Illustration
below. Related supplement and circuit description are given in the following.

COMPRESSOR
lC4b

MODE X1

010
-o

01-04

_¢
-o

011
MODE X2

/\/\

05-08

End address

S/H The data in the preceding cycle are

lC21a A/D read from these cells and routed to

ICZZa, b IC19 registers of IC17.

IC17
Comparator
IL DlN DOUT
m» u-lolelololololslolololol-->
llllllllllllllllllllll b' Startaddress/
SAH

LPFs

The role of the first LPF (01-04, 05-08) in the input stage is to prevent
aliasing or foldover which takes place when the sampling (SAH) frequency in
the analog-to-digital conversion is less than twice the frequency components
of the waveform being sampled. The LPF rolls off unnecessary high frequen-
cy components of the input signal.

Since the sampling frequency is halved when MODEx2 is ON the LPF in-
cludes two filters of different cut-off frequency; one of which is choosen
when 010 or 011 is turned ON by a control signal from SW MATRIX, ac-
cording to the position of MODE (SW3).

The configuration and function of the second LPF (015-017, 018-020) in
the output stage are similar to those of the first, and the purpose is to smooth
out jagged, staircase shape (digital component) of analog-converted delay sig-
nal.

COMPR ESSOR AND EXPANDER

These are fabricated on one-chip IC, and called "compander" as a whole.
Since the dynamic range of input signal is compressed by the compressor, the
actual range of voltage the A/D converter can cover is extended. Also, the
voltages of the delay signal are restored to the original dynamic range by the
expander, and the S/N ratio of delay signal is further improved.

A/D CONVERTER

This circuit is intended to obtain digital data equivalent to analog voltage by
comparing the voltage value of sampled analog signal with multiple voltage
data already known. The A/D conversion employed in the DE-200 is a succes-
sive approximation. it is similar to measuring the length of a column (sampled
pulse voltage) by joining several rods with different lengths (whose lengths are
known but no scale is provided: digital data).

Suppose the sampled signal voltage is 8V (column length: 8m), and the
maximum voltage handled by A/D converter is 20V (20m). Then, one rod
(MSB) from SAR in |Cl7 is applied through D11 pin to R205 (ladder resis-
tor), where it is cut to a length of 20+2 = 10m (1/2 of the maximum voltage

(IC17)

These 3 bits are temporarily buffered until the remaining 9 bits are given.
All 12 bits are delivered to R205 in parallel format at the same time.

|
I
l
|
l
I comes elongated.
|
l
l
.
.
i

Memory cells not used for data storage
The number is reduced as the setting of delay time range be-

ll
pg

E

SJQJSIBBJ 1

MAR. 20, 1984

.._______-______J

_____ -.-.-.-~-______

| Halved when MODEX2 is ON.

| Varies by 1-2 times with Delay Time Fine.

I.___...._- _______ _._.....-_

that can be covered by A/D converter) and is compared on 1019 pin 3 with
the column on pin 2.

The rod is longer than the column but it has no scale necessary for the meas-
urement. Therefore, it is returned to SAR. (IC19 pin 7 goes H, MSB of SAR
is reset, and D11 pin becomes L.) Next, the 2nd register of SAR is set to ap-
ply the rod from D10 pin to R205 where it is cut to a length of 5m (1/2 of
M33). Since the rod is shorter than the 8m column, it is kept as it is (lC19
pin 7 output "L), and the output from 09, cut to 2.5m (NI-EB), is joined to
the rod. The total length of the rod is still shorter than the column, and
therefore the output (1.25m) of D8 is added to it. Then the total length of
the rod will be 5 + 2.5 +1.25 = 8.75m that is longer than the column. 80, the
last rod is returned to SAR (D8 goes "L").

In this way, rods, each exactly one-half the length of its preceding stage, are
added in order down to LSB, and those (bits) that cause the total length of
rods to become longer than the column are reset. This way of processing
makes the total length of rods added becoming extremely proximate to the
length of the column. The registers of SAR are not used as data storage but
for the comparison. The outputs from comparator lCiQ are used to set or
reset each register of SAR and are also delivered as serial data from D OUT
pin to RAMs lC13-IC15 and stored in memory cells.

1 The operating tempo of each circuit within these stages I
Constant through delay time range settings.

...._.___
I

MHLLLLLLIMLLULU
SAH
EXPANDER
lC4a
LPF eye 015
I
020 017
023 1 L024
MODE x2 MODE X1

DELAY

RAM MEMORY CELLS

S/H J'L

lC22

SOUND